V-shaped flash memory structure

ABSTRACT

A flash memory having a V-shaped stack gate structure. The V-shaped stack gate is formed by implanting ions into a substrate to form a buried source line using a mask, and then forming a V-shaped trench that exposes the buried source line in the substrate. A V-shaped word line stack gate is next formed over the trench and the substrate next to the trench. A common drain terminal is formed in the substrate on each side of the V-shaped stack gate. The drain terminal is electrically connected to a bit line by forming a contact plug.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the priority benefit of Taiwan application Ser. No. 89105151, filed Mar. 21, 2000.

BACKGROUND OF THE INVENTION

[0002] 1. Field of Invention

[0003] The present invention relates to a semiconductor device structure. More particularly, the present invention relates to a V-shaped flash memory structure.

[0004] 2. Description of Related Art

[0005] Conventional non-volatile memory can be divided into several types including erasable programmable read only memory (EPROM), electrical erasable programmable read only memory (EEPROM) and flash memory. Because input data are retained when power is turned off, they are ideal storage media for operational programs.

[0006] In general, a flash memory unit includes a floating gate for storing electric charges and a control gate for controlling the access of data. The floating gate is formed in the space within the control gate. The floating gate is normally in a floating state because the gate is not connected to any external circuit. On the other hand, the control gate is electrically connected to a word line and the drain terminal of a flash memory unit is electrically connected to a bit line.

[0007] To program data into a flash memory unit, electrons are injected into the floating gate unit near the drain terminal through a channel hot electron injection (CHEI). To erase data from a flash memory unit, electrons in the floating gate are channeled away via a source terminal through Fowler-Nordheim (FN) tunneling. For a flash memory unit having a conventional N-type ETOX structure, injection probability in a CHEI operation is only about 10⁻⁹. Hence, a higher voltage must be applied resulting in greater energy consumption and lower programming efficiency.

[0008] In addition, due to an increase in the level of integration, dimensions of each device in a silicon chip will decrease according to the design rules. Consequently, operating voltage of a device is also lowered correspondingly. Since a large coupling between the floating gate and the control gate will lower the voltage needed to operate a memory transistor, it is beneficial to increase the capacitance between a floating gate and a control gate.

[0009] There are three methods of increasing capacitor coupling between a floating gate and a control gate. They includes increasing the overlapping area between the floating gate and the control gate, decreasing the thickness of dielectric layer between the floating gate and the control gate and increasing the dielectric constant k of the dielectric layer. However, the dielectric layer between the floating gate and the control gate must have sufficient thickness to prevent trapped electrons in the floating gate from jumping into the control gate leading to device failure. On the other hand, increasing dielectric constant of the dielectric layer is not a simple task because it involves materials and techniques that are closely related to processing equipment.

SUMMARY OF THE INVENTION

[0010] Accordingly, one object of the present invention is to provide a V-shaped flash memory structure capable of increasing the level of integration as well as efficiency in programming and erasing. Furthermore, through an increase in the overlapping area between the floating gate and the control gate in each flash memory cell, capacitor coupling is increased and operating voltage is lowered.

[0011] The invention provides a V-shaped flash memory cell structure. The flash memory cell structure is formed above a substrate. The structure at least includes a source terminal, a tunnel oxide layer, a floating gate, a dielectric layer, a control gate and a common drain terminal. The source terminal is buried within the substrate. The tunnel oxide layer is formed above the substrate. The tunnel oxide layer has a V-shaped wedge section embedded in the substrate, whose tip is connected to the source terminal. In addition, the tunnel oxide layer has two side wings that extend from the upper comers on each side of the V-shaped wedge section. The floating gate is above the tunnel oxide layer and has a profile conformal to the tunnel oxide layer. The dielectric layer is above the floating gate and has a profile conformal to the floating gate. The control gate is above the dielectric layer. The common drain region is in the substrate next to the tunnel oxide layer.

[0012] The V-shaped structure of this invention increases the level of integration of flash memory and the overlapping area between the floating gate and the control gate. Hence, capacitor coupling is increased and operating voltage is lowered. In addition, the provision of two channels in the V-shaped structure increases programming and erasing efficiency of each flash memory unit.

[0013] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

[0015]FIG. 1 is a schematic top view showing the layout of a flash memory unit according to one preferred embodiment of this invention;

[0016]FIGS. 2A through 2F are schematic cross-sectional views along line I-I′ of FIG. 1 showing the progression of steps for producing the flash memory unit according to this invention;

[0017]FIG. 3 is a cross-sectional view related to FIG. 2F showing how sidewall spacers are used to increase the width of a word line contact plug;

[0018]FIG. 4 is a cross-sectional view showing the flash memory structure according to this invention; and

[0019]FIG. 5 is an equivalent circuit diagram of an array of flash memory units each having a V-shaped gate structure according to this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0021]FIG. 1 is a schematic top view showing the layout of a flash memory unit according to one preferred embodiment of this invention. As shown in FIG. 1, a plurality of longitudinal device isolation structures 102 such as field oxide or shallow trench isolation (STI) is formed in a semiconductor substrate 100. The device isolation structures 102 provide the necessary isolation between adjacent flash memory cells. A source line SL is embedded within the substrate 100 (FIG. 2A) and connected to a column address register at the peripheral region of the memory cell array. The V-shaped word line stack gate WL structure is formed above the buried source line SL. The word line stack gate WL is also connected to the column address register at the peripheral region of the memory cell array. A bit line BL is electrically connected to the drain region (location of the contact plug 146) in the substrate 100 on each side of word line WL via a contact plug 146. The bit line BL runs in a direction vertical to the word line stack gate WL and the buried source line SL. The bit line BL is electrically connected to a row address register at the peripheral region of the memory cell array. Through proper selection of word line WL, source line SL and bit line BL, a particular memory cell (the memory cell in area A) may be selected for programming, reading or data erasure.

[0022] Since the buried source line SL is formed beneath the word line WL, some layout area for the source line is saved. Because each flash memory unit in this invention has a smaller dimension than the flash memory unit in a conventional flash memory layout, overall level of integration of the flash memory is greatly increased.

[0023]FIGS. 2A through 2F are schematic cross-sectional views along line I-I′ of FIG. 1 showing the progression of steps for producing the flash memory unit according to this invention.

[0024] First, as shown in FIG. 2A, a substrate 100 is provided. Device isolation structures 102, for example, field oxide (FOX) layers or shallow trench isolation (STI) structures are formed in the substrate 100. A hard mask layer 114 and mask spacers 118 are formed over the substrate 100. The hard mask layer 114 and the mask spacers 118 can be formed using silicon nitride, for example. In addition, a buffer layer 112 is formed in the space between the hard mask layer 114 and the substrate 100 while another buffer layer 116 is formed between the mask spacer 118 and the hard mask layer 114. These buffer layers 112 and 116 lower the stress between the hard mask layer 114 and the mask spacers 118. The hard mask layer 114, the mask spacers 118 together with the buffers 112 and 116 are formed by sequentially depositing silicon oxide and silicon nitride over the substrate 100 to form a silicon oxide and a silicon nitride layer. Through conventional photolithographic and etching processes, the oxide layer and nitride layer are patterned to form the buffer layer 112 and the hard mask layer 114. A conformal silicon oxide layer and a silicon nitride layer are next formed over the substrate 100. Finally, the conformal oxide layer and the conformal nitride layer are sequentially etched to form the buffer 116 and the mask spacers 118.

[0025] As shown in FIG. 2B, an ion implantation is conducted implanting ions into the substrate 100 to form a buried source line 120 while using the hard mask layer 114 and the mask spacers 118 as a mask. Depth of the buried source line 120 can be adjusted according to the dimensions of the desired flash memory unit. For example, if the width of separation w between two neighboring mask spacers 118 is 0.15 μm, implanted depth of the source line 120 should be between 0.2 to 0.4 μm.

[0026] As shown in FIG. 2C, using the hard mask layer 114 and the mask spacers 118 as a mask, V-shaped trench 122 is formed in the substrate 100. A slant-etching technique, for example, is used to etch the substrate 100 such that the bottom section of the V-shaped trench 122 is ultimately in contact with the source line 120. The bottom section of the V-shaped trench may be flattened somewhat due to local processing conditions. However, a flattening of the trench bottom is unlikely to have any serious effect on the structure or performance of the flash memory.

[0027] As shown in FIG. 2D, the hard mask layer 114, the mask spacers 118 and the buffer layer 112 and 116 are removed. If the mask layers are nitride layers and the buffer layers are oxide layers, the nitride layers are removed by phosphoric acid (H₃PO₄) solution while the oxide layers are removed by diluted hydrogen fluoride (HF) solution.

[0028] A V-shaped word line stack gate structure 130 is formed above the V-shaped trench 122. The word line stack gate 130 includes a tunnel oxide layer 132, a floating gate 134, a dielectric layer 136 and a control gate 138. Since a conventional word line stack is directly formed over the substrate, no V-shaped structure is formed. The lower portion of the stack gate structure 130 has a V-shaped profile because a V-shaped trench 122 is formed in a previous step.

[0029] The stack gate structure 130 is formed in a manner very similar to the fabrication of the stack gate of a conventional ETOX flash memory. For example, a conformal silicon oxide layer and a conformal doped polysilicon layer are sequentially formed over the substrate 100 to serve as the tunnel oxide layer 132 and the floating gate 134. Conventional photolithographic and etching techniques are next used to pattern the oxide layer and the doped polysilicon layer. Hence, a plurality of parallel conductive lines perpendicular to the buried source line 120 (buried source line SL in FIG. 1) is formed in the active region between the device isolation structures 102. A thin conformal dielectric layer such as an oxide-nitride-oxide (ONO) layer is formed over the doped polysilicon layer, and then another doped polysilicon layer is formed over the dielectric layer. The ONO layer serves as the dielectric layer 136 while the second doped polysilicon layer serves as the control gate 138. Finally, the stack of layers is patterned to form a plurality of parallel word lines 130 above the buried source lines 120. The tunnel oxide layer 132 and the floating gate 134 are formed above the active region of each memory unit. On the other hand, the dielectric layer 136 and the control gate 138 are connected in series with the tunnel oxide layer 112 and floating gate 114 above the buried source line 120.

[0030] As shown in FIG. 2E, an anti-punchthrough implant is carried out, implanting ions into the substrate 100 between adjacent stack gates 130 to form an anti-punchthrough dopant region 140. Depth of implant is roughly at the same level as the buried source line 120. However, the implanted dopants should have a polarity just opposite to the dopants inside the buried source line 120. For example, if the implanted dopants inside the buried source line are N-type (such as phosphorus or arsenic), the implanted dopants inside the anti-punchthrough dopant region 140 should be P-type (such as boron). Similarly, another ion implantation is conducted, implanting dopants having polarity type similar to the one in the source line into substrate between adjacent stack gates 130 to form a common drain region 142.

[0031] As shown in FIG. 2F, an insulation layer 144 such as a silicon oxide layer is formed over the substrate 100. The insulation layer can be a silicon oxide layer formed, for example, in a chemical vapor deposition using tetra-ethyl-ortho-silicate (TEOS). A chemical-mechanical polishing is next carried out to planarize the insulation layer 144. Contact plugs 146 that connect electrically to the drain region 142 are formed in the insulation layer 144. A plurality of parallel bit lines 148 is formed over the insulation layers 144 for linking up rows of contact plugs 146. The bit lines 148 run in a direction perpendicular to the stack gates 130. The contact plug 146 is formed by performing photolithographic and etching operation to form a contact opening in the insulation layer 144, and then depositing conductive material into the opening to form the contact plug 146. Conductive material for filling the opening includes sputtered tungsten (W) or aluminum (Al). Alternatively, the conductive material can be doped polysilicon formed by chemical vapor deposition. The bit lines 148 are formed by conventional photolithographic and etching techniques.

[0032]FIG. 3 is a cross-sectional view related to FIG. 2F showing how sidewall spacers are used to increase the width of a word line contact plug. Beside using the aforementioned method of forming the contact plug 146, a cap layer 150 and sidewall spacers 152 can be used to form a contact plug 156 that has a larger process window. The method includes forming a cap layer 150 such as a silicon nitride layer over the stack gates 130, and then forming spacers 152 on the sidewalls of the word line stack gates 130 and the cap layer 150. An insulation layer 154 is formed over the substrate 100. Contact openings are formed in the insulation layer 154 by conventional photolithographic and etching techniques. Conductive material is deposited into the contact opening to form the contact plug, and then a bit line is formed over the contact plug. The etching step for forming the contact window is a self-aligned process due to the presence of an etch-resistant cap layer 150 and sidewall spacers 152. Since a wider photoresist opening can be used in a self-aligned process, processing window of the contact plug is increased.

[0033]FIG. 4 is a cross-sectional view showing the flash memory structure according to this invention. As shown in FIG. 4, the components of a flash memory cell includes a V-shaped word line stack gate structure 130, a source line 120 near the tip section of the V-shaped structure, and a common drain 142 between two adjacent V-shaped word line stack gates 130. The V-shaped word line stack gate 130 includes a V-shaped wedge section 210 buried within the substrate 100 and connected to the buried source line 120. In other words, the tip 212 at the bottom of the V-shaped wedge section 210 is enclosed by a portion of the buried source line 120. In addition, a wing 220 is formed above the substrate 100 extending from a corner region 214 on each side of the V-shaped wedge section 210. The common drain terminal 142 is formed in the substrate 100 on each side of the stack gate 130 next to its neighboring word line stack gate 130.

[0034] Since the word line stack gate 130 is formed from a tunnel oxide layer 132, a floating gate 134, a dielectric layer 136 and a control gate 138, the tunnel oxide layer 132 has a portion of V-shaped wedge section 210 buried within the substrate 100 and connected with the buried source line 120. In other words, the tip 212 of the V-shaped wedge section 210 is enclosed by the buried source line 120. Moreover, the V-shaped wedge section 210 has two side wings 220 each extending from the corner regions 214 on each side of the V-shaped wedge section 210. The floating gate layer 134 is above the tunnel oxide layer 132 conformal to the underlying tunnel oxide layer 132. Similarly, the floating gate layer 134 also has a V-shaped wedge section 210 and side wings 220. The dielectric layer 136 is above the floating gate 134 and conformal to the underlying floating gate 134.

[0035] The word line stack gate of a conventional ETOX flash memory is laid horizontally over the substrate. For such a layout, overlapping area between a floating gate and its overlying control gate depends on the surface area of the floating gate. Since coupling capacitance depends on the effective surface area of a capacitor, coupling of flash memory cell will be reduced following any reduction in the dimension of the flash memory unit.

[0036] The flash memory cell of this invention has a V-shaped word line stack gate structure buried within a substrate. Through bending in the vertical direction, overlapping area between the floating gate and the control gate is increased, and the operating voltage of the stack gate is lowered. In fact, the overlapping area between the floating gate and the control gate in this invention is more than twice that of a conventional ETOX flash memory. Moreover, by forming a buried bit line directly under the word line stack gate, layout area for source line is greatly reduced. Hence, the level of integration for flash memory having this V-shaped stack gate structure is increased.

[0037]FIG. 5 is an equivalent circuit diagram of an array of flash memory units each having a V-shaped gate structure according to this invention. In FIG. 5, the circled flash memory unit A has the same configuration as the enclosed flash memory unit A shown in FIG. 1. The flash memory of this invention inputs data into a flash memory unit by channel hot electron injection (CHEI) while erasing data from the flash memory unit by Fowler-Nordheim (FN) tunneling. The following is a brief description of the mode of operation of an N-type flash memory.

[0038] To program data into a selected flash memory unit, a positive voltage such as Vcc is applied to word line WL2 and a higher positive voltage such as 2 Vcc is applied to bit line BL1. A zero voltage (ground voltage) is applied to other non-selected word lines WL1 and WL3, bit line BL2 and source lines SL1, SL2 and SL3 respectively. Through channel hot electron injection, electric charges are injected into the floating gate. Depending on whether electrons are injected into the floating gate or not, the respective flash memory cell are programmed.

[0039] Since electric charges are injected into the floating gate by hot electron injection, electrons coming from the source terminal will speed across to the drain terminal and the floating gate. Electrons propelled from the source terminal are accelerated along the channel. With the aid of the corner region (indicated by label 160 in FIG. 2F) on the V-shaped wedge section, electrons jump from the neighborhood of the corner region 160 straight into the floating gate 134. Hence, the injection probability is greatly increased, thereby saving programming energy.

[0040] To erase data from a selected flash memory unit, a negative voltage is applied to the word line WL2 and a positive voltage is applied to the source line SL2. A zero voltage is applied to other non-selected word lines WL1 and WL3, source lines SL1 and SL3, and bit lines BL1 and BL2. Through a Fowler-Nordheim (FN) tunneling effect, electrons trapped inside the floating gate are pulled out.

[0041] While FN tunneling is occurring to erase data within a flash memory unit, two channels are formed on each side of the V-shaped structure of this invention. Since a conventional flash memory cell normally has just one channel, speed of erasure is doubled.

[0042] To read data from a selected flash memory unit, a positive voltage such as Vcc is applied to the word line and a smaller positive voltage such as 0.2 Vcc to 0.02 Vcc is applied to the bit line. A zero voltage is applied to the source line. Through such an arrangement, data inside the flash memory unit can be readily read out. Because each flash memory unit has two channels, reading current is roughly double that of a conventional unit. Hence, reading stability for this type of flash memory unit is increased.

[0043] In summary, the advantages of the invention include:

[0044] (1) By forming the word line stack gate over the buried source line, layout area required by each memory cell is reduced. Hence, overall level of integration of the flash memory is increased.

[0045] (2) By forming a V-shaped word line gate structure, overlapping area between the floating gate and the control gate is increased, thereby increasing coupling capacitance and lowering operating voltage.

[0046] (3) Each flash memory cell actually has two channels. Therefore, efficiency of memory erase is increased. In addition, since reading current is almost doubled, reading stability is also improved considerably.

[0047] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents. 

What is claimed is:
 1. A flash memory cell having a V-shaped gate above a substrate, comprising: a source terminal buried within the substrate; a tunnel oxide layer above the substrate having a V-shaped wedge section enclosed by the substrate and a wing section extended from the side near the upper comers of the V-shaped wedge, wherein the tip of the V-shaped wedge is in contact with the source terminal; a floating gate above the tunnel oxide layer conformal to the surface profile of the underlying tunnel oxide layer; a dielectric layer above the floating gate conformal to the surface profile of the underlying floating gate; a control gate above the dielectric layer; and a common drain terminal in the substrate adjacent to and on each side of the tunnel oxide layer.
 2. The structure of claim 1, wherein the source terminal includes an ion doped region.
 3. The structure of claim 1, wherein a material for forming the floating gate includes doped polysilicon.
 4. The structure of claim 1, wherein the dielectric layer includes a composite stack consisting of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer.
 5. The structure of claim 1, wherein a material for forming the control gate includes doped polysilicon.
 6. The structure of claim 1, wherein the common drain terminal includes an ion doped region.
 7. A flash memory cell having a V-shaped gate above a substrate, comprising: a V-shaped stack gate having a V-shaped wedge section enclosed by the substrate and two wing sections above the substrate extending from an upper corner region on each side of the V-shaped wedge; a source terminal buried within the substrate, which source terminal also encloses a tip of the V-shaped wedge; and a common drain terminal in the substrate adjacent to and on each side of the V-shaped stack gate.
 8. The structure of claim 7, wherein the V-shaped stack gate includes a conformal tunnel oxide layer, a floating gate, a dielectric layer and a control gate.
 9. The structure of claim 8, wherein material for forming the floating gate includes doped polysilicon.
 10. The structure of claim 8, wherein the dielectric layer includes a composite stack consisting of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer.
 11. The structure of claim 8, wherein material for forming the control gate includes doped polysilicon.
 12. The structure of claim 7, wherein the source terminal includes an ion doped region.
 13. The structure of claim 7, wherein the common drain terminal includes an ion doped region. 